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AD1893JN Scheda tecnica(PDF) 5 Page - Analog Devices |
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AD1893JN Scheda tecnica(HTML) 5 Page - Analog Devices |
5 / 20 page AD1893 REV. A –5– AD1893 PIN LIST Serial Input Interface Pin Name DIP LQFP I/O Description DATA_I 3 43 I Serial input, MSB first, containing two channels of 4 to 16 bits of twos-complement data per channel. BCLK_I 4 2 I Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion. WCLK_I 5 3 I Word clock input for input data. This input is rising edge sensitive. (Not required in LR input data clock triggered modes.) LR_I 6 4 I Left/right clock input for input data. Must run continuously. Serial Output Interface Pin Name DIP LQFP I/O Description DATA_O 23 30 O Serial output, MSB first, containing two channels of 4- to 24-bits of twos-complement data per channel. BCLK_O 26 35 I Bit clock input for output data. Need not run continuously; may be gated or used in a burst fashion. WCLK_O 25 32 I Word clock input for output data. This input is rising edge sensitive. (Not required in LR output data clock triggered modes.) LR_O 24 31 I Left/right clock input for output data. Must run continuously. Input Control Signals Pin Name DIP LQFP I/O Description BKPOL_I 10 9 I Bit clock polarity. LO: Normal mode. Input data is sampled on rising edges of BCLK_I. HI: Inverted mode. Input data is sampled on falling edges of BCLK_I. MODE0_I 11 10 I Serial mode zero control for input port. MODE1_I 12 13 I Serial mode one control for input port. MODE0_I MODE1_I 0 0 Left-justified, no MSB delay, LR_I clock triggered. 0 1 Left-justified, MSB delay, LR_I clock triggered. 1 0 Right-justified, MSB delayed 16 bit clock periods from LR_I transition. 1 1 WCLK_I triggered, no MSB delay. PIN CONFIGURATIONS DIP 1 2 3 7 8 9 10 11 12 4 5 6 13 14 28 27 26 22 21 20 19 18 17 25 24 23 16 15 SERIAL IN SERIAL OUT COEF ROM MULT FIFO CLOCK TRACKING ACCUM XTAL_I DATA_I BCLK_I WCLK_I VDD GND NC BKPOL_I MODE0_I MODE1_I GND RESET L R_I SETSLW PWRDWN BCLK_O WCLK_O DATA_O VDD GND NC BKPOL_O MODE0_O MODE1_O MUTE_O MUTE_I L R_O AD1893 NC = NO CONNECT XTAL_O LQFP NC = NO CONNECT NC WCLK_O NC VDD GND DATA_O NC BCLK_I NC VDD GND WCLK_I BKPOL_O MODE0_O NC NC BKPOL_I MODE0_I NC NC 44 39 38 33 40 41 42 28 27 26 43 31 30 29 32 AD1893 25 24 23 21 22 18 20 19 12 13 15 16 17 14 1 2 6 4 5 3 7 8 11 9 10 36 35 34 37 L R_I L R_O SERIAL IN MULT FIFO ACCUM CLOCK TRACKING SERIAL OUT COEF ROM |
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