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ADF41020BCPZ-RL7 Scheda tecnica(PDF) 6 Page - Analog Devices

Il numero della parte ADF41020BCPZ-RL7
Spiegazioni elettronici  The ADF41020 frequency synthesizer can be used to implement local oscillators as high as 18 GHz in the up conversion and down conversion sections of wireless receivers and transmitters.
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

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ADF41020
Data Sheet
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 3, 5, 9, 10
GND
Ground Pins.
4
RF
IN
Input to the RF Prescaler. This input is ac-coupled internally.
6, 7
AV
DD
Analog Power Supply. This may range from 2.85 V to 3.15 V. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin. Pin 6 is the supply for the fixed divide-by-4 prescaler.
8
REF
IN
Reference Input. This is a CMOS input with a nominal threshold of DV
DD/2 and a dc equivalent input
resistance of 100 kΩ (see Figure 9). This input can be driven from a TTL or CMOS crystal oscillator or it
can be ac-coupled.
11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high powers up the device, depending on the status of the power-down bit, PD1.
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This is a high impedance CMOS input.
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high
impedance CMOS input.
14
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches with the latch being selected using the control bits.
15
MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
16, 17
DV
DD
Digital Power Supply. This may range from 2.85 V to 3.15 V. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin. DV
DD must be the same value as AVDD.
18
V
P
Charge Pump Power Supply.
19
R
SET
Connecting a resistor between this pin and GND sets the maximum charge pump output current.
The nominal voltage potential at the R
SET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAX
CP
R
I
5
.
25
=
So, with R
SET = 5.1 kΩ, ICP MAX = 5.0 mA.
20
CP
Charge Pump Output. When enabled, this provides ±I
CP to the external loop filter, which in turn drives the
external VCO.
EP
Exposed Pad. The exposed pad must be connected to GND.
14
13
12
1
3
4
LE
15 MUXOUT
DATA
CLK
11 CE
GND
GND
2
GND
RFIN
5
GND
TOP
VIEW
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GND.
ADF41020


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