Data Sheet

ADF41020

Rev. 0 | Page 9 of 16

R COUNTER

The 14-bit R counter allows the input reference frequency to

be divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383

are allowed.

PFD AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 13 is a simplified schematic.

The PFD includes a fixed delay element that controls the

width of the antibacklash pulse. This pulse ensures that there

is no dead zone in the PFD transfer function and minimizes

phase noise and reference spurs. The charge pump converts the

PFD output to current pulses, which are integrated by the PLL

loop filter.

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF41020 allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 in the function

latch. Figure 17 shows the full truth table. Figure 12 shows

the MUXOUT section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect:

digital lock detect and analog lock detect.

Digital lock detect is active high. Digital lock detect is set high

when the phase error on five consecutive phase detector cycles

is less than 15 ns. It stays set high until a phase error of greater

than 25 ns is detected on any subsequent PD cycle.

Figure 12. MUXOUT Circuit

INPUT SHIFT REGISTER

The ADF41020 digital section includes a 24-bit input shift

register, a 14-bit R counter, and a 19-bit N counter, comprising

a 6-bit A counter and a 13-bit B counter. Data is clocked into

the 24-bit shift register on each rising edge of CLK. The data is

clocked in MSB first. Data is transferred from the shift register

to one of three latches on the rising edge of LE. The destination

latch is determined by the state of the two control bits (C2, C1)

in the shift register. C2 and C1 are the two LSBs, DB1 and DB0,

as shown in the timing diagram of Figure 2. The truth table for

these bits is shown in Table 5. Table 5 shows a summary of

how the latches are programmed. The SPI is both 1.8 V and

3 V compatible.

Table 5. C1, C2 Truth Table

Control Bits

Data Latch

C2

C1

0

0

R counter

0

1

N counter (A and B)

1

0

Function latch (including prescaler)

Figure 13. PFD Simplified Schematic

GND

CONTROL

MUX

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

MUXOUT

HIGH

HIGH

D1

D2

Q1

Q2

CLR2

CP

U1

U2

UP

DOWN

GND

U3

R DIVIDER

FIXED

DELAY

N DIVIDER

CHARGE

PUMP

CLR1