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FM24V01-GTR Scheda tecnica(PDF) 10 Page - Cypress Semiconductor

Il numero della parte FM24V01-GTR
Spiegazioni elettronici  128Kb Serial 3V F-RAM Memory
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Produttore elettronici  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM24V01-GTR Scheda tecnica(HTML) 10 Page - Cypress Semiconductor

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FM24V01 - 128Kb I2C FRAM
Rev. 3.0
Jan. 2012
Page 10 of 14
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
Ratings
VDD
Power Supply Voltage with respect to VSS
-1.0V to +4.5V
VIN
Voltage on any pin with respect to VSS
-1.0V to +4.5V
and VIN < VDD+1.0V *
TSTG
Storage Temperature
-55C to +125C
TLEAD
Lead Temperature (Soldering, 10 seconds)
260 C
VESD
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
3.5kV
1.25kV
200V
Package Moisture Sensitivity Level
MSL-1
* Exception: The “V
IN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40 C to + 85 C, VDD =2.0V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
Notes
VDD
Main Power Supply
2.0
3.3
3.6
V
IDD
VDD Supply Current
@ SCL = 100 kHz
@ SCL = 1 MHz
@ SCL = 3.4 MHz
90
200
500
175
400
1000
A
A
A
1
ISB
Standby Current
80
150
A
2
IZZ
Sleep Mode Current
4
8
A
2
ILI
Input Leakage Current
±1
A
3
ILO
Output Leakage Current
±1
A
3
VIL
Input Low Voltage
-0.3
0.3 VDD
V
VIH
Input High Voltage
0.7 VDD
VDD + 0.3
V
VOL1
Output Low Voltage (IOL = 2 mA, VDD ≥ 2.7V)
0.4
V
VOL2
Output Low Voltage (IOL = 150 A)
0.2
V
RIN
Address Input Resistance (WP, A2-A0)
For VIN = VIL (max)
For VIN = VIH (min)
50
1
K
M
4
Notes
1.
SCL toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V.
2.
SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3.
VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins.
4.
The input pull-down circuit is stronger (50K) when the input voltage is below VIL and weak (1M) when the input voltage
is above VIH.


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