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FM24C04B-G Scheda tecnica(PDF) 9 Page - Cypress Semiconductor |
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FM24C04B-G Scheda tecnica(HTML) 9 Page - Cypress Semiconductor |
9 / 12 page FM24C04B Rev. 3.0 Jan. 2012 Page 9 of 12 AC Parameters (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V, CL = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz tLOW Clock Low Period 4.7 1.3 0.6 s tHIGH Clock High Period 4.0 0.6 0.4 s tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 s tBUF Bus Free Before New Transmission 4.7 1.3 0.5 s tHD:STA Start Condition Hold Time 4.0 0.6 0.25 s tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 s tHD:DAT Data In Hold 0 0 0 ns tSU:DAT Data In Setup 250 100 100 ns tR Input Rise Time 1000 300 300 ns 1 tF Input Fall Time 300 300 100 ns 1 tSU:STO Stop Condition Setup 4.0 0.6 0.25 s tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CI/O Input/Output Capacitance (SDA) 8 pF 1 CIN Input Capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. Power Cycle Timing VDD min. VDD SDA,SCL tVR tPD tPU tVF Power Cycle Timing (TA = -40C to +85C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes tPU Power Up (VDD min) to First Access (Start condition) 10 - ms tPD Last Access (Stop condition) to Power Down (VDD min) 0 - s tVR VDD Rise Time 30 - s/V 1 tVF VDD Fall Time 30 - s/V 1 Notes 1. Slope measured at any point on VDD waveform. |
Codice articolo simile - FM24C04B-G |
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Descrizione simile - FM24C04B-G |
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