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74LVX74SJ Scheda tecnica(PDF) 5 Page - Fairchild Semiconductor

Il numero della parte 74LVX74SJ
Spiegazioni elettronici  Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74LVX74SJ Scheda tecnica(HTML) 5 Page - Fairchild Semiconductor

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©1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX74 Rev. 1.4.0
5
AC Electrical Characteristics
Note:
3. Parameter guaranteed by design tOSLH = |tPLHm–tPLHn|, tOSHL = |tPHLm–tPHLn|
Capacitance
Note:
4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load.
Average operating current can be obtained by the eqation: ICC(opr.) =
Symbol
Parameter
VCC (V)
CL (pF)
TA = +25°C
TA = –40°C to
+85°C
Units
Min.
Typ.
Max.
Min.
Max.
tPLH, tPHL
Propagation Delay,
CPn to Qn or Qn
2.7
15
7.3
15
1.0
18.5
ns
50
9.8
18.5
1.0
22
3.3 ± 0.3
15
5.7
9.7
1.0
11.5
50
8.2
13.2
1.0
15
tPLH, tPHL
Propagation Delay,
CDn to SDn to Qn or Qn
2.7
15
8.4
15.6
1.0
18.5
ns
50
10.9
19.1
1.0
22
3.3 ± 0.3
15
6.6
10.1
1.0
12
50
9.1
13.6
1.0
15.5
tW
CPn or CDn or SDn Pulse
Width
2.7
8.5
10
ns
3.3 ± 0.3
6
7
tS
Setup Time, Dn to CPn
2.7
8.0
9.5
ns
3.3 ± 0.3
5.5
6.5
tH
Hold Time, Dn to CPn
2.7
0.5
0.5
ns
3.3 ± 0.3
0.5
0.5
tREC
Recovery Time,
CPn or SDn to CPn
2.7
6.5
7.5
ns
3.3 ± 0.3
5.0
5.0
fMAX
Maximum Clock
Frequency
2.7
15
55
135
50
MHz
50
45
60
40
3.3 ± 0.3
15
95
145
80
50
60
85
50
tOSLH, tOSHL Output to Output Skew
(3)
2.7
50
1.5
1.5
ns
3.3
1.5
1.5
Symbol
Parameter
TA = +25°C
TA = –40°C to
+85°C
Units
Min.
Typ.
Max.
Min.
Max.
CIN
Input Capacitance
4
10
10
pF
CPD
Power Dissipation Capacitance(4)
25
pF
C
PD
V
CC
f
IN
I
CC
×
×
×
2 per F F
,
()
---------------------------------------------------------


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