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TC62D748CFG Scheda tecnica(PDF) 5 Page - Toshiba Semiconductor |
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TC62D748CFG Scheda tecnica(HTML) 5 Page - Toshiba Semiconductor |
5 / 23 page TC62D748CFG 2011-12-14 5 Truth Table SCK SLAT OE SIN OUT0 … OUT7 … OUT15 (Note1) SOUT H L Dn Dn … Dn − 7 … Dn − 15 Dn − 15 L L Dn + 1 No Change Dn − 14 H L Dn + 2 Dn + 2 … Dn − 5 … Dn − 13 Dn − 13 − (Note2) L Dn + 3 Dn + 2 … Dn − 5 … Dn − 13 Dn − 13 − (Note2) H Dn + 3 OFF Dn − 13 Note1: When OUT0 to OUT15 output pins are set to "H" the respective output will be ON and when set to "L" the respective output will be OFF. Note2: “-“ is irrelevant to the truth table. Timing Diagram ・ The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit. ・ Keep the SLAT pin is set to “L” to enable the latch circuit to hold data. In addition, when the SLAT pin is set to “H” the latch circuit does not hold data. The data will instead pass onto output. When the OE pin is set to “L” the OUT0 to OUT15 output pins will go ON and OFF in response to the data. In addition, when the OE pin is set to “H” all the output pins will be forced OFF regardless of the data. ・ This product can use 3.3V and 5.0V power supply, but power supply and input (SCK/SIN/ SLAT / OE ) must use same voltage. SIN SLAT SCK OUT0 OUT1 SOUT OE OUT15 H L n = 0 1 2 3 4 5 6 8 H L H L H L ON OFF ON OFF ON OFF ON OFF H L 79 11 10 12 13 15 14 2 OUT |
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