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CXA2108Q Scheda tecnica(PDF) 6 Page - Sony Corporation |
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CXA2108Q Scheda tecnica(HTML) 6 Page - Sony Corporation |
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6 / 28 page  – 6 – CXA2108Q DGND DVCC 19 16 13 20 17 14 52 18 15 READY signal output. This indicates the drive current data RAM access enabled period. Access is enabled while high level is output. (See the Timing Charts.) DLDI signal output. This outputs the DLDI signal synchronized with CLK. Write ALL signal output. One pulse (= high level signal with a width of 1 clock) is output synchronized with the rising edge of the next CLK after the final address∗1 of the currently selected mode is input. Note that both the final address must be input and the XCS and XWR input levels must be low at the rising edge of this CLK. (See the Timing Charts for details.) ∗1 02Fh (Upper/Lower mode) 08Fh (Upper/Lower/RGB mode) Upper signal output. This is used as the LED switching signal. (See the Timing Charts and Application Circuits for details.) Test signal output. This pin is unrelated to the functions of this IC. Do not connect anything; leave this pin open. Blue signal output. This is used as the LED switching signal. (See the Timing Charts and Application Circuits for details.) Red signal output. This is used as the LED switching signal. (See the Timing Charts and Application Circuits for details.) Green signal output. This is used as the LED switching signal. (See the Timing Charts and Application Circuits for details.) Thermal Alarm Out signal output. This pin normally outputs high level, but it outputs low level when the internal temperature rises to an abnormally high level. 13 RDY CMOS O 14 DLDO CMOS O 15 WALL CMOS O 16 XUPR CMOS O 17 TEST_O CMOS O 18 XB CMOS O 19 XR CMOS O 20 XG CMOS O 52 XTAO CMOS O Pin No. Symbol Equivalent circuit Description Reference voltage level I/O |
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