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MC100E136FNG Scheda tecnica(PDF) 9 Page - ON Semiconductor |
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MC100E136FNG Scheda tecnica(HTML) 9 Page - ON Semiconductor |
9 / 12 page MC10E136, MC100E136 http://onsemi.com 9 Figure 6. Programmable Divider Waveforms S1 COUT CLOCK DIVIDE BY 37 LOAD 000000 000001 000010 000011 100010 100011 100100 • •• ••• ••• LOAD The exercise of building a programmable divider then becomes simply determining what value to load into the counter to accomplish the desired division. Since the load operation requires a clock pulse, to divide by N, N−1 must be loaded into the counter. A single E136 device is capable of divide ratios of 2 to 64 inclusive, Table 1 outlines the load values for the various divide ratios. Figure 4 presents the waveforms resulting from a divide by 37 operation. Note that the availability of the COUT complementary output COUT allows the user to choose the polarity of the divide by output. For single device programmable counters the E016 counter is probably a better choice than the E136. The E016 has an internal feedback to control the reloading of the counter, this not only simplifies board design but also will result in a faster maximum count frequency. For programmable dividers of larger than 8 bits the superiority of the E016 diminishes, and in fact for very wide dividers the E136 will provide the capability of a faster count frequency. This potential is a result of the cascading features mentioned previously in this document. Figure 5 shows the architecture of a 24-bit programmable divider implemented using E136 counters. Note the need for one external gate to control the loading of the entire counter chain. An ideal device for the external gating of this architecture would be the 4-input OR function in the 8-lead SOIC ECLinPS Lite™ family. However the final decision as to what device to use for the external gating requires a balancing of performance needs, cost and available board space. Note that because of the need for external gating the maximum count frequency of a given sized programmable divider will be less than that of a single cascaded counter. Figure 7. 24-bit Programmable Divider Architecture S1 S1 S1 S1 Q0 −> Q5 D0 −> D5 CLK Q0 −> Q5 D0 −> D5 CLK Q0 −> Q5 D0 −> D5 CLK LSB Q0 −> Q5 D0 −> D5 CLOUT COUT CLIN CIN CLK CLOCK “LO” “LO” “LO” CLOUT COUT CLIN CIN CLOUT COUT CLIN CIN MSB CLOUT COUT CLIN CIN OUT |
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