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CS8363 Scheda tecnica(PDF) 4 Page - ON Semiconductor

Il numero della parte CS8363
Spiegazioni elettronici  3.3 V Dual Micropower Regulator with ENABLE and RESET
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Produttore elettronici  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS8363 Scheda tecnica(HTML) 4 Page - ON Semiconductor

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CS8363
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PACKAGE PIN DESCRIPTION
PACKAGE PIN #
PIN SYMBOL
FUNCTION
D2PAK−7
1
VSTBY
Standby output voltage delivering 100 mA.
2
VIN
Input voltage.
3
VTRK
Tracking output voltage controlled by ENABLE delivering 250 mA.
4
GND
Reference ground connection.
5
Adj
Resistor divider from VTRK to Adj. Sets the output voltage on VTRK. If tied to
VTRK, VTRK will track VSTBY.
6
ENABLE
Provides on/off control of the tracking output, active LOW.
7
RESET
CMOS compatible output lead that goes low whenever VSTBY falls out of
regulation.
CIRCUIT DESCRIPTION
ENABLE Function
The ENABLE function switches the output transistor for
VTRK on and off. When the ENABLE lead voltage exceeds
1.4 V (Typ), VTRK turns off. This input has several hundred
millivolts of hysteresis to prevent spurious output activity
during power−up or power−down.
RESET Function
The RESET is an open collector NPN transistor,
controlled by a low voltage detection circuit sensing the
VSTBY (3.3 V) output voltage. This circuit guarantees the
RESET output stays below 1.0 V (0.1 V Typ) when VSTBY
is as low as 1.0 V to ensure reliable operation of
microprocessor−based systems.
VTRK Output Voltage
This output uses the same type of output device as VSTBY,
but is rated for 250 mA. The output is configured as a
tracking regulator of the standby output. By using the
standby output as a voltage reference, giving the user an
external programming lead (Adj lead), output voltages from
3.3 V to 20 V are easily realized. The programming is done
with a simple resistor divider, and following the formula:
VTRK + VSTBY
(1 ) R1 R2) ) IAdj
R1
If another 3.3 V output is needed, simply connect the Adj
lead to the VTRK output lead.
C1*
0.1 mF
GND
CS8363
MCU
B+
VIN
VTRK
Adj
ENABLE
RESET
VSTBY
R3
VDD
C2**
10 mF
ESR < 8.0 W
3.3 V, 100 mA
RESET
I/O
R2
R1
C3**
10 mF
ESR < 8.0 W
SW 5.0 V,
250 mA
GND
VTRK ∼ VSTBY(1 + R1/R2)
For VTRK ∼ 5.0 V, R1/R2 ∼ 0.5
*C1 is required if regulator is located far from power supply filter.
**C2 and C3 are required for stability.
Figure 2. Test and Application Circuit, 3.3 V, 5.0 V Regulator


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