– 2 –

CXA1782CQ/CR

Block Diagram

RF IV AMP1

•FCS PHASE COMPENSATION

•TRACKING

PHASE COMPENSATION

•I SET

•I IL DATA REGISTER •INPUT SHIFT REGISTER

•ADRESS.DECODER

•WINDOW COMP.

2

3

4

5

6

11

12

1

7

8

9

10

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

40

APC

FE AMP

F IV AMP

TE AMP

E IV AMP

RF IV AMP2

LEVEL S

FOK

MIRR

DFCT

I IL

TTL

I IL

TTL

I IL

TTL

•OUTPUT DECODER

TOG1 to 3

BAL1 to 3

FS1 to 4 TG1 to 2 TM1 to 7

PS1 to 4

LPF COMP

HPF COMP

TM6

TM5

TM4

TM3

TM7

TM2

TG1

TM1

DFCT

TZC COMP

FS4

DFCT

ATSC

FZC COMP

FS1

FS2

TG2

FE_BIAS

F

E

EI

TEO

LPFI

ATSC

TEI

TZC

VC

TDFCT

SENS

C.OUT

XRST

DATA

XLT

CLK

Vcc

SL_O

ISET

SL_M

TA_O

SL_P

• The switch state in Block Diagram is for initial resetting.

• Switch turns to side for 1 and to side for 0 in Serial Data Truth Table.

• DFCT switch turns to side when defect signal generates for DEFECT = E in Serial Data Truth Table.

• TG1 switch turns to side and TG2 switch is left open when TG1 and TG2 (address 1 : D3) is 1.

°

°

°

•