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BU1852GUW-E2 Scheda tecnica(PDF) 5 Page - Rohm |
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BU1852GUW-E2 Scheda tecnica(HTML) 5 Page - Rohm |
5 / 26 page Technical Note 5/25 BU1852GUW, BU1852GXW www.rohm.com 2012.08 - Rev.B © 2012 ROHM Co., Ltd. All rights reserved. 5. Startup sequence Fig.3 Start Sequence timing VDD=1.8V, VDDIO=1.8V, Topr=25℃, TW=VSS Parameter Symbol Limits Unit Conditions Min. Typ. Max. VDD Stable Time tVDD - - 5 ms VDD and VDDIO are ON at the same time. Reset Wait Time tRWAIT 0 - - µs XRST controlling※ 1 Reset Valid Time tRV 10 - - µs I 2C Wait Time tI2CWAIT 10 - - µs ※ 1 Even if XRST port is not used, it operates because Power On Reset is built in. In this case, connect XRST port with VDD on the set PCB. Note) At VDD=0V, when SCL port is changed from 0V to 0.5V or more, SCL port pulls the current. It is same in SDA, XINT, and ROW[7:0] ports of 3V tolerant I/O. (VDDIO=0V in case of COL[11:0] ports) Fig.4 Port operating at VDD=0V VDD VDDIO XRST SCL SDA tVDD tVDD tRWAIT tI2CWAIT tRV tI2CWAIT tVDD tRWAIT tVDD VDD Port (~2kΩ Pull-up) 0V 3V Port Pull Current 2~3ms 0.1~1mA 0V |
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