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74HC373-Q100 Scheda tecnica(PDF) 5 Page - NXP Semiconductors |
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74HC373-Q100 Scheda tecnica(HTML) 5 Page - NXP Semiconductors |
5 / 24 page 74HC_HCT373_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 10 August 2012 5 of 24 NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state 6. Functional description 6.1 Function table [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values [1] For SO20: Ptot derates linearly with 8 mW/K above 70 C. [2] For TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C. [3] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C. Table 3. Function table[1] Operating mode Control Input Internal latches Output OE LE Dn Qn Enable and read register (transparent mode) LH LL L HH H Latch and read register L L l L L hH H Latch register and disable outputs H XXX Z Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7 V IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO >VCC +0.5 V - 20 mA IO output current VO = 0.5 V to (VCC +0.5 V) - 35 mA ICC supply current - +70 mA IGND ground current - 70 mA Tstg storage temperature 65 +150 C Ptot total power dissipation SO20 package [1] - 500 mW TSSOP20 package [2] 500 mW DHVQFN20 package [3] - 500 mW |
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