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CXA1315M Scheda tecnica(PDF) 7 Page - Sony Corporation |
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CXA1315M Scheda tecnica(HTML) 7 Page - Sony Corporation |
7 / 11 page – 7 – CXA1315M/P <Registers> In brackets ( ) number of bits REF (1) : Switches D/A converter reference voltage 0: Standardizes the inner regulator 1: Standardizes voltage resistance divided from Vcc SW0 to 3 (1) : Selects ON/OFF of Pins 1, 2, 9 and 10 (Each pin is the open collector output of NPN transistor) 0: OFF 1: ON DAC0 to 4 (8) : Digital data input register of D/A converter 0: Output voltage turns to minimum 255: Output voItage turns to maximum PONRES (1) : Detects POWER ON RESET 0: Master passes from the bus and is reset to "0" after having read this status 1: Sets to "1" when power supply is turned on or when there has been a power dip ST0 to 3 (1) : Detects and registers the voltage condition of Pins 1, 2, 9 and 10 0: 1.5V and below 1: 3.0V and above Note) SW0 to 3 effective during "0" I2C Bus Signal There are 2 signals in I2C bus. SDA (Serial Data) and SCL (Serial Clock). SDA is double-way. • As SDA is bidirectional it has 3 state outputs, H, L and Hi-Z. • I2C transfer begins with Start Condition and ends with Stop Condition. SDA SCL Start Condition S Stop Condition P H L Hi-Z L |
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