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CXA1315M Scheda tecnica(PDF) 4 Page - Sony Corporation |
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CXA1315M Scheda tecnica(HTML) 4 Page - Sony Corporation |
4 / 11 page CXA1315M/P SW, SAD Pins 8 8 9 10 11 Low level input voItage High level input voltage Low level input current High level input current Low level input voltage VIL VIH IIL IIH VOL Input voltage where ST0 to ST3 become "0" Input voltage where ST0 to ST3 become "1" lnput current when 0.4V is applied lnput current when 4.5V is applied SW 0 to 3 = 1, Output voltage when 1mA flows in 4 4 4 4 5 — 3.0 –10 –10 0 — — 0 0 0.2 1.5 — +10 +10 0.4 V V µA µA V No. Item Symbol Test conditions Min. Test circuit Typ. Max. Unit I2C Bus Block Items (SDA, SCL) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO 3.0 0 — — 0 3 — 0 4.7 4.0 4.7 4.0 4.7 5 250 — — 4.7 — — — — — — — — — — — — — — — — — — 5.0 1.5 10 10 0.4 — 10 100 — — — — — — — 1 300 — V V µA µA V mA pF kHz µs µs µs µs µs µs ns µs ns µs No. Item Symbol Min. Typ. Max. Unit High level input voltage Low level input voltage High level input current Low level input current Low level output voltage, at 3mA flow to SDA (Pin 14) Maximum flowing current lnput capacitance Maximum clock frequency Data change minimum waiting time Data transfer start minimum waiting time Low level clock pulse width High level clock pulse width Minimum start preparation waiting time Minimum data hold time Minimum data preparation time Rise time Fall time Minimum stop preparation waiting time I2C bus load conditions: Pull-up resistance 4k Ω (Connected to +5V) Load capacitance 200pF (Connected to GND) I2C Bus Control Signal tLOW tBUF tHD; STA tR tHD; DAT tHIGH tSU; DAT tF tHD; STA tSU; STA tSU; STO SDA SCL PS Sr P – 4 – |
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