SN74HC273Q1

OCTAL DTYPE FLIPFLOP

WITH CLEAR

SCLS578A − MARCH 2004 − REVISED APRIL 2008

4

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25°C

MIN

MAX

UNIT

VCC

MIN

MAX

MIN

MAX

UNIT

2 V

5

4

fclock

Clock frequency

4.5 V

27

18

MHz

fclock

Clock frequency

6 V

32

21

MHz

2 V

80

120

CLR low

4.5 V

16

24

tw

Pulse duration

CLR low

6 V

14

20

ns

tw

Pulse duration

2 V

80

120

ns

CLK high or low

4.5 V

16

24

CLK high or low

6 V

14

20

2 V

100

150

Data

4.5 V

20

30

tsu

Setup time before CLK

↑

Data

6 V

17

25

ns

tsu

Setup time before CLK

↑

2 V

100

150

ns

CLR inactive

4.5 V

20

30

CLR inactive

6 V

17

25

2 V

0

0

th

Hold time, data after CLK

↑

4.5 V

0

0

ns

th

Hold time, data after CLK

6 V

0

0

ns

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25°C

MIN

MAX

UNIT

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

UNIT

2 V

5

11

4

fmax

4.5 V

27

50

18

MHz

fmax

6 V

32

60

21

MHz

2 V

55

160

240

tPHL

CLR

Any

4.5 V

15

32

48

ns

tPHL

CLR

Any

6 V

12

27

41

ns

2 V

56

160

240

tpd

CLK

Any

4.5 V

15

32

48

ns

tpd

CLK

Any

6 V

13

27

41

ns

2 V

38

75

110

tt

Any

4.5 V

8

15

22

ns

tt

Any

6 V

6

13

19

ns

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance per flip-flop

No load

35

pF