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SN74GTLPH32912ZKFR Scheda tecnica(PDF) 1 Page - Texas Instruments |
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SN74GTLPH32912ZKFR Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 17 page www.ti.com FEATURES DESCRIPTION SN74GTLPH32912 36-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES379A – JANUARY 2002 – REVISED MAY 2005 • LVTTL Outputs (–24 mA/24 mA) • Member of the Texas Instruments Widebus+™ • GTLP Rise and Fall Times Designed for Family Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in • Ioff, Power-Up 3-State, and BIAS VCC Support Transparent, Latched, Clocked, and Live Insertion Clock-Enabled Modes • Bus Hold on A-Port Data Inputs • TI-OPC™ Circuitry Limits Ringing on • Distributed VCC and GND Pins Minimize Unevenly Loaded Backplanes High-Speed Switching Noise • OEC™ Circuitry Improves Signal Integrity and • Latch-Up Performance Exceeds 100 mA Per Reduces Electromagnetic Interference JESD 78, Class II • Bidirectional Interface Between GTLP Signal • ESD Protection Exceeds JESD 22 Levels and LVTTL Logic Levels – 2000-V Human-Body Model (A114-A) • LVTTL Interfaces Are 5-V Tolerant – 200-V Machine Model (A115-A) • Medium-Drive GTLP Outputs (50 mA) – 1000-V Charged-Device Model (C101) The SN74GTLPH32912 is a medium-drive, 36-bit UBT™ transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 Ω. GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH32912 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+, UBT, TI-OPC, OEC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2002–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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