www.ti.com

FEATURES

DESCRIPTION/ORDERING INFORMATION

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED JUNE 2005

•

Variable Edge-Rate Control (ERC) Input

Selects GTLP Rise and Fall Times for Optimal

•

Member of the Texas Instruments Widebus+™

Data-Transfer Rate and Signal Integrity in

Family

Distributed Loads

•

TI-OPC™ Circuitry Limits Ringing on

•

Unevenly Loaded Backplanes

Live Insertion

•

OEC™ Circuitry Improves Signal Integrity and

•

Bus Hold on A-Port Data Inputs

Reduces Electromagnetic Interference

•

•

Bidirectional Interface Between GTLP Signal

High-Speed Switching Noise

Levels and LVTTL Logic Levels

•

Latch-Up Performance Exceeds 100 mA Per

•

LVTTL Interfaces Are 5-V Tolerant

JESD 78, Class II

•

High-Drive GTLP Outputs (100 mA)

•

LVTTL Outputs (–24 mA/24 mA)

The SN74GTLPH3245 is a high-drive, 32-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL

signal-level translation. It is partitioned as four 8-bit transceivers. The device provides a high-speed interface

between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed

(about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced

output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC

circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and

tested using several backplane models. The high drive allows incident-wave switching in heavily loaded

backplanes with equivalent load impedance down to 11

Ω.

GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard

JESD 8-3. The ac specification of the SN74GTLPH3245 is given only at the preferred higher noise-margin GTLP,

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,

reference voltage.

circuitry disables the outputs, preventing damaging current backflow through the device when it is powered

down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power

connections, preventing disturbance of active data on the backplane during card insertion or removal, and

permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated

backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal

integrity, which allows adequate noise margin to be maintained at higher frequencies.

High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC

optimize system data-transfer rate and signal integrity to the backplane load.

Active bus-hold circuitry is provided to hold unused or undriven LVTTL data inputs at a valid logic state. Use of

pullup or pulldown resistors with the bus-hold circuitry is not recommended.

through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the

driver.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus+, TI-OPC, OEC, TI are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 1999–2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.