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CDCM61001RHBR Scheda tecnica(PDF) 1 Page - Texas Instruments |
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CDCM61001RHBR Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 34 page CDCM61001 www.ti.com SCAS869F – FEBRUARY 2009 – REVISED JUNE 2011 One Output, Integrated VCO, Low-Jitter Clock Generator Check for Samples: CDCM61001 – Two Pins for Prescaler/Feedback Divider 1 FEATURES – Three Pins for Output Divider 2 • One Crystal/LVCMOS Reference Input – Two Pins for Output Select Including 24.8832 MHz, 25 MHz, and 26.5625 MHz • Chip Enable and Device Reset Control Pins Available • Input Frequency Range: 21.875 MHz to 28.47 MHz • 3.3-V Core and I/O Power Supply • On-Chip VCO Operates in Frequency Range of • Industrial Temperature Range: –40°C to +85°C 1.75 GHz to 2.05 GHz • 5-mm × 5-mm, 32-pin, QFN (RHB) Package • 1x Output Available: • ESD Protection Exceeds 2 kV (HBM) – Pin-Selectable Between LVPECL, LVDS, or 2-LVCMOS; Operates at 3.3 V APPLICATIONS • LVCMOS Bypass Output Available • Low Jitter Clock Driver for High-End Datacom • Output Frequency Selectable by /1, /2, /3, /4, /6, Applications Including SONET, Ethernet, Fibre /8 from the Output Divider Channel, Serial ATA, and HDTV • Supports Common LVPECL/LVDS Output • Cost-Effective High-Frequency Crystal Frequencies: Oscillator Replacement – 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz, 106.25 MHz, 125 MHz, 150 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz, DESCRIPTION 187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz, The CDCM61001 is a highly versatile, low-jitter 311.04 MHz, 312.5 MHz, 622.08 MHz, frequency synthesizer that can generate low-jitter 625 MHz clock outputs, selectable between low-voltage • Supports Common LVCMOS Output positive emitter coupled logic (LVPECL), low-voltage Frequencies: differential signaling (LVDS), or low-voltage – 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, complementary metal oxide semiconductor 100 MHz, 106.25 MHz, 125 MHz, 150 MHz, (LVCMOS) outputs, from a low-frequency crystal or 155.52 MHz, 156.25 MHz, 159.375 MHz, LVCMOS input for a variety of wireline and data 187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz communication applications. The CDCM61001 • Output Frequency Range: 43.75 MHz to features an onboard PLL that can be easily 683.264 MHz (See Table 3) configured solely through control pins. The overall output random jitter performance is less than 1ps, • Internal PLL Loop Bandwidth: 400 kHz RMS (from 10 kHz to 20 MHz), making this device a • High-Performance PLL Core: perfect choice for use in demanding applications such – Phase Noise typically at –146 dBc/Hz at as SONET, Ethernet, Fibre Channel, and SAN. The 5-MHz Offset for 625-MHz LVPECL Output CDCM61001 is available in a small, 32-pin, 5-mm × – Random Jitter typically at 0.509 ps, RMS 5-mm QFN package. (10 kHz to 20 MHz) for 625-MHz LVPECL Output • Output Duty Cycle Corrected to 50% ( ± 5%) • Divider Programming Using Control Pins: 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2009–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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