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BU21021GUL-E2 Scheda tecnica(PDF) 7 Page - Rohm |
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BU21021GUL-E2 Scheda tecnica(HTML) 7 Page - Rohm |
7 / 13 page Datasheet Datasheet 7/10 TSZ02201-0Y1Y0F300060-1-2 © 2012 ROHM Co., Ltd. All rights reserved. 19.Jun.2012 Rev.001 www.rohm.com TSZ22111・15・001 BU21021GUL ●HOST-I/F timing specification (4-wire SPI) (Note: SCK=SCL_SCK, SI=SDA_SI, CSB=SEL_CSB and SO=SO) 4-wire SPI has the burst write and burst read. The automatic address increment is done until 0x5F. After address 0x5F is accessed, it is not changed. WA6 WA5 WA4 WA3 WA2 WA1 WA0 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 WD7 WD6 WD1 WD0 RA6RA5 RA4RA3 RA2 RA1 RA0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 RD7 RD6 RD1 RD0 RD7 CSB SCK SI write SI read SO read Register address Write (WA) Write (WA + 1) Write (WA + n) Register address Read (RA) Read (RA + 1) Read (RA + n) HiZ HiZ t1 t2 t3 t4 t5 t8 t9 t6 t7 W/R W/R Figure 5. Timing specification (4-wire SPI) Table 1. Timing Requirements: 4-wire SPI at VDD = 3.0V, Ta = 25℃ Parameter Symbol Rating Unit Conditions Min Typ Max CSB setup time t1 30 - - ns ‘H’ width of SCK t2 30 - - ns ‘L’ width of SCK t3 30 - - ns SI setup time t4 20 - - ns SI holding time t5 20 - - ns CSB holding time t6 20 - - ns ‘H’ width of CSB t7 50 - - ns SO output delay time t8 - - 15 ns SCK frequency t9 - - 15 MHz |
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