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TPA2054D4A Scheda tecnica(PDF) 3 Page - Texas Instruments |
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TPA2054D4A Scheda tecnica(HTML) 3 Page - Texas Instruments |
3 / 30 page Bias Control and Pop Suppression 1mF OUTR– OUTR+ Mode Control HPLEFT HPRIGHT SDA I2C Interface SCL Charge Pump 1mF 1mF CPP CPN VSS VDDHP PGND OUTL– OUTL+ VDD Gain Select: +6 dB 0 dB -6 dB -14 dB -66dB to +24dB Volume Control Headphone Power Limiter VDDHP VSS VDDHP VSS RESET LIN- LIN+ RIN- RIN+ 0.47mF 0.47mF 0.47mF 0.47mF +6 dB VDD PGND +6 dB VDD PGND PWM H- Bridge Oscillator PWM H- Bridge 1mF VREF MONO– MONO+ 0.47mF 0.47mF DVDD + – -66dB to +24dB Volume Control Power on Reset Bias Control and Pop Suppression 1mF OUTR– OUTR+ Mode Control HPLEFT HPRIGHT SDA I2C Interface SCL Charge Pump 1mF 1mF CPP CPN VSS VDDHP PGND OUTL– OUTL+ VDD Gain Select: +6 dB 0 dB -6 dB -14 dB -66dB to +24dB Volume Control -66dB to +24dB Volume Control Headphone Power Limiter VDDHP VSS VDDHP VSS RESET RIN1 LIN1 RIN2 LIN2 0.47mF 0.47mF 0.47mF 0.47mF +6 dB VDD PGND +6 dB VDD PGND PWM H- Bridge Oscillator PWM H- Bridge 1mF VREF MONO– MONO+ 0.47mF 0.47mF DVDD + – -66dB to +24dB Volume Control Power on Reset TPA2054D4A www.ti.com SLOS666 – MAY 2010 FUNCTIONAL BLOCK DIAGRAM Figure 1. Differential Input Mode Figure 2. Single-Ended (SE) Input Mode Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TPA2054D4A |
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