TEA1792ATS datasheet(5/13 Pages) NXP

Il numero della parte	TEA1792ATS

Spiegazioni elettronici	GreenChip synchronous rectifier controller

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TEA1792ATS

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Objective data sheet

Rev. 1 — 10 August 2012

5 of 13

NXP Semiconductors

TEA1792ATS

GreenChip synchronous rectifier controller

The level of the driver regulation voltage Vreg(drv) can be selected using the SELREG pin.

When this SELREG pin is grounded, the typical Vreg(drv) equals 42 mV. When the

SELREG pin is left open, the Vreg(drv) level equals 30 mV.

Internally, the SELREG pin has a pull-up current source of 10

A. When this pin is short

circuited to ground, the pin selects the lowest Vreg(drv). If the pin is left open, the highest

Vreg(drv) value is selected.

If the secondary stroke of the flyback converter is shorter than tact(sr)(min) short time (0.8 s

typical), the driver output is disabled. This action guarantees stable operation for very low

duty cycles. When the secondary stroke increases above tact(sr)(min), long time (0.95 s

typical), the driver output is again enabled.

7.4 Supply management

All internal reference voltages are derived from a temperature compensated, on-chip

band gap circuit.

7.5 Driver

The driver circuit to the external power MOSFET gate has a typical source capability of

400 mA and a typical sink capability of 2.7 A. These capabilities permit fast switch-on and

switch-off of the power MOSFET for efficient operation. The source stage is coupled to the

timer (see Figure 1). When the timer has finished, the source capability is reduced to a

small current (5 mA typical) capable of keeping the driver output voltage at its level.

Fig 3.

Synchronous rectification signals

aaa-000137

0 V

Vdeact(drv) (-12 mV typ.)

Vreg(drv) (-42 mV/-30 mV typ.)

Vact(drv) (-220 mV typ.)

0 A

0 V

VSRSENSE

VDRIVER

primary

current

secondary

current

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