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SN74GTL2010PWE4 Scheda tecnica(PDF) 2 Page - Texas Instruments |
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SN74GTL2010PWE4 Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 18 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) GTL2010 10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR SCDS221 – SEPTEMBER 2006 All transistors in the GTL2010 have the same electrical characteristics, and there is minimal deviation from one output to another in voltage or propagation delay. This offers superior matching over discrete transistor voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being identical, the reference transistor (SREF/DREF) can be located on any of the other ten matched Sn/Dn transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides excellent ESD protection. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING –40 °C to 85°C TSSOP – PW Tape and reel SN74GTL2010PWR GK2010 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. PIN DESCRIPTION PIN NO. NAME DESCRIPTION 1 GND Ground (0 V) 2 SREF Source of reference transistor 3–12 Sn Ports S1–10 13–22 Dn Ports D10–D1 23 DREF Drain of reference transistor 24 GREF Gate of reference transistor 2 Submit Documentation Feedback |
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