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SN74AUP2G32 Scheda tecnica(PDF) 2 Page - Texas Instruments |
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SN74AUP2G32 Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 20 page 1 2 7 1A 1B 1Y 5 6 3 2A 2B 2Y SN74AUP2G32 SCES754B – SEPTEMBER 2009 – REVISED MAY 2010 www.ti.com The SN74AUP2G32 performs the Boolean function Y = A + B or Y = A\ • B\ in positive logic. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE(1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3) NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP2G32YFPR _ _ _ H G _ 0.23-mm Large Bump – YFP (Pb-free) uQFN – DQE Reel of 5000 SN74AUP2G32DQER PS –40°C to 85°C QFN – RSE Reel of 5000 SN74AUP2G32RSER PS SSOP – DCU Reel of 3000 SN74AUP2G32DCUR H32_ (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (3) DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE (EACH GATE) INPUTS OUTPUT Y A B H X H X H H L L L LOGIC DIAGRAM (POSITIVE LOGIC) Pin numbers shown are for DCU and DQE packages. 2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G32 |
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