SN74AHCT244Q

OCTAL BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SGDS024 – FEBRUARY 2002

1

POST OFFICE BOX 655303

Requirements

Can Be Supported Along with

Major-Change Approval

CMOS) Process

JESD 17

description

This octal buffer/driver is designed specifically to

improve both the performance and density of

3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74AHCT244Q is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs.

When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are

in the high-impedance state.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

40

°Cto125°C

SOIC – D

Tape and reel

SN74AHCT244QDWR

AHCT244Q

–40

°C to 125°C

TSSOP – PW

Tape and reel

SN74AHCT244QPWR

HB244Q

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each 4-bit buffer/driver)

INPUTS

OUTPUT

OE

A

Y

L

H

H

L

LL

H

X

Z

Copyright

 2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments.

1

2

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7

8

9

10

20

19

18

17

16

15

14

13

12

11

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

2OE

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

DW OR PW PACKAGE

(TOP VIEW)