DEVICE RESET

OPERATING CHARACTERISTICS

TPA2054D4

Figure 3. SCL and SDA Timing

Figure 4. Start and Stop Conditions Timing

This clears the LIM_Lock bit to logic low, allowing changes to the headphone output limiter byte. Refer to the

Register Map section for a complete list of default states. The I2C registers cannot be programmed until RESET

returns to logic high. RESET requires a 1 ms minimum hold time at logic low for a valid reset command.

On power-up, ensure that the DVDD and VDDHP voltages have settled and DVDD is at least 1.7V before setting

RESET to logic high. The TPA2054D4 activates in soft shutdown mode, SWS bit at logic high.

MODE[2:0] = 001 (single-ended mode)(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER AMPLIFIER

700

mW

Speaker output power

860

mW

940

mW

Offset Voltage

–13

5

13

mV

Output impedance in shutdown

2

k

Ω

SNR

Signal-to-noise ratio

90

dB

Noise output voltage

Total gain = 0 dB; A-weighted

22

µV

RMS

0.18

%

THD+N

Total harmonic distortion plus noise

0.25

%

6

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