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SL74LVU04N Scheda tecnica(PDF) 4 Page - System Logic Semiconductor |
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SL74LVU04N Scheda tecnica(HTML) 4 Page - System Logic Semiconductor |
4 / 6 page SL74LVU04 4 System Logic Semiconductor SLS V min max min max min max IIH High-Level Input Leakage Current VI= VÑÑ 5.5 - 0.1 - 1.0 - 1.0 ICC Quiescent Supply Current (per Package) VI=0 Â or VÑÑ IO = 0 ìA 5.5 - 4.0 - 20 - 40 ìA ICC1 Additional Quiescent Supply Current on input VI = VÑÑ - 0.6V 2.7 3.6 - - 0.2 0.2 - - 0.5 0.5 - - - 0.85 0.85 mA AC ELECTRICAL CHARACTERISTICS (C L=50 pF, tLH =tHL = 2.5 ns, RL=1 kÙ) Guaranteed Limit 25 °C -40 °C ÷ 85°C -40 °C ÷ 125°C Symbol Parameter Test Conditions VCC V Min max min max min max Unit tPHL (tPLH) Propagation Delay, Input A to Output Y (Figure 1 ) VI=0 V or V1 tLH = tHL =2.5 ns ÑL = 50 pF RL = 1 kÙ 1.2 2.0 2.7 3.0 4.5 - - - - - 70 22 16 13 11 - - - - - 80 26 19 15 13 - - - - - 100 31 23 18 16 ns CI Input Capacitance 5.5 - 7.0 - - - - pF ÒÀ=25 °Ñ, V I=0V or VCC pF CPD Power Dissipation Capacitance (Per Inverter) 36 Used to determine the no-load dynamic power consumption: PD = CPDVCC 2f I+ (CLVCC 2fo), f I - input frequency, fo - output frequency (MHz) (CLVCC 2fo) – sum of the outputs |
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