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SL74LV573 Scheda tecnica(PDF) 1 Page - System Logic Semiconductor |
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SL74LV573 Scheda tecnica(HTML) 1 Page - System Logic Semiconductor |
1 / 6 page SL74LV573 System Logic Semiconductor SLS OCTAL D-TYPE TRANSPARENT LATCH (3-State) By pinning SL74LV573 are compatible with SL74HC573 and SL74HCT573 series. Input voltage levels are compatible with stadard CMOS levels. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Voltage supply range from 1.2 to 5.5 V • LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ • Output current 8 mÀ • Latch current: not less than150 mÀ at Ò = 125 °Ñ • ESD acceptable value: not less than 2000 V as per HBM and not less than 200 V as per MM FUNCTION TABLE Inputs Outputs OE LE D Q L H H H L H L L L L X no change H X X Z H -HIGH voltage level L - LOW voltage level X - don’t care Z - High impedance state ORDERING INFORMATION SL74LV573N Plastic DIP SL74LV573D SOIC TA = -40 ° to 125° C for all packages PIN ASSIGNMENT 1 2 3 5 4 6 7 8 9 10 VCC 20 18 17 16 15 14 19 11 12 13 GND OE D0 D1 D2 Q1 Q0 Q2 D3 D4 D5 D6 Q3 Q4 Q5 Q6 Q7 LE D7 |
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