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DAC5674 Scheda tecnica(PDF) 3 Page - Texas Instruments |
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DAC5674 Scheda tecnica(HTML) 3 Page - Texas Instruments |
3 / 39 page DAC5674 SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005 www.ti.com 3 DC ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 20 mA, Rset = 1.91 kΩ, internal reference, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION 14 Bits DC ACCURACY(1) INL Integral nonlinearity 1 LSB = IOUTFS/214, TMIN to TMAX −3.5 3.5 LSB INL Integral nonlinearity 1 LSB = IOUTFS/214, TMIN to TMAX −2.14e−4 2.14e−4 IOUTFS DNL Differential nonlinearity −2 2 LSB DNL Differential nonlinearity −1.22e−4 1.22e−4 IOUTFS Monotonicity Montonic to 12 bits ANALOG OUTPUT Offset error 0.02 FSR Gain error Without internal reference 2.3 %FSR Gain error With internal reference 1.3 %FSR Minimum full-scale output current(2) 2 mA Maximum full-scale output current(2) 20 mA Output compliance range(3) IOUTFS = 20 mA −1 1.25 V Output resistance 300 k Ω Output capacitance 5 pF REFERENCE OUTPUT Reference voltage 1.14 1.2 1.26 V Reference output current(4) 100 nA REFERENCE INPUT VEXTIO Input voltage range 0.1 1.25 V Input resistance 1 M Ω Small signal bandwidth 1.4 MHz Input capacitance 100 pF TEMPERATURE COEFFICIENTS Offset drift 0 ppm of FSR/ °C Gain drift Without internal reference ±50 ppm of FSR/ °C Gain drift With internal reference ±100 ppm of FSR/ °C Reference voltage drift ±50 ppm/ °C POWER SUPPLY AVDD Analog supply voltage 3 3.3 3.6 V DVDD Digital supply voltage 1.65 1.8 1.95 V CLKVDD Clock supply voltage 3 3.3 3.6 V IOVDD I/O supply voltage 1.65 3.6 V PLLVDD PLL supply voltage 3 3.3 3.6 V IAVDD Analog supply current Including output current through the load resistor, AVDD = 3.3 V, DVDD = 1.8 V, 4 × interpolation, PLL on, 9-MHz IF, 400 MSPS 41 55 mA Specifications subject to change without notice. (1) Measured differentially across IOUT1 and IOUT2 into 50 Ω. (2) Nominal full-scale current, IOUTFS, equals 32× the IBIAS current. (3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC5674 device. The upper limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity. (4) Use an external buffer amplifier with high impedance input to drive any external load. |
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