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CD74HC40103-EP Scheda tecnica(PDF) 5 Page - Texas Instruments |
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CD74HC40103-EP Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 14 page CD74HC40103EP HIGHSPEED CMOS LOGIC 8STAGE SYNCHRONOUS DOWN COUNTER SCLS548 − DECEMBER 2003 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER VCC TA = 25°C MIN MAX UNIT PARAMETER VCC MIN MAX MIN MAX UNIT 2 V 165 250 CP 4.5 V 33 50 CP 6 V 28 43 2 V 125 190 tw Pulse duration PL 4.5 V 25 38 ns tw Pulse duration PL 6 V 21 32 ns 2 V 125 190 MR 4.5 V 25 38 MR 6 V 21 32 2 V 3 2 fmax CP frequency (see Note 4) 4.5 V 15 10 MHz fmax CP frequency (see Note 4) 6 V 18 12 MHz 2 V 100 150 P to CP 4.5 V 20 30 P to CP 6 V 17 26 2 V 75 110 PE to CP 4.5 V 15 22 tsu Setup time PE to CP 6 V 13 19 ns tsu Setup time 2 V 150 225 ns TE to CP 4.5 V 30 45 TE to CP 6 V 26 38 2 V 50 75 To CP, MR inactive 4.5 V 10 15 To CP, MR inactive 6 V 9 13 2 V 5 5 P to CP 4.5 V 5 5 P to CP 6 V 5 5 2 V 0 0 th Hold time TE to CP 4.5 V 0 0 ns th Hold time TE to CP 6 V 0 0 ns 2 V 2 2 PE to CP 4.5 V 2 2 PE to CP 6 V 2 2 NOTE 4: Noncascaded operation only. With cascaded counters, clock-to-terminal count propagation delays, count enables (PE or TE) to clock setup times, and count enables (PE or TE) to clock hold times determine maximum clock frequency. For example, with these HC devices: CP fmax + 1 CP to TC prop delay ) TE to CP setup time ) TE to CP hold time + 1 60 ) 30 ) 0 [ 11 MHz |
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