SL74HC4052D datasheet(5/9 Pages) SLS

Il numero della parte	SL74HC4052D

Spiegazioni elettronici	Analog Multiplexer/Demultiplexer(High-Performance Silicon-Gate CMOS)

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Produttore elettronici	SLS [System Logic Semiconductor]

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SL74HC4052

System Logic

Semiconductor

SLS

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V)

VCC

VEE

Limit

*

Symbol

Parameter

Test Conditions

V

25

°C

Unit

BW

Maximum On-

Channel

Bandwidth or

Minimum

Frequency

Response

(Figure 5)

fin=1 MHz Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VOS

Increase fin Frequence Until dB Meter

Reads -3 dB

RL =50

Ω, C

L=10 pF

2.25

4.50

6.00

-2.25

-4.50

-6.00

95

MHz

-

Off-Channel

Feedthrough

Isolation

(Figure 6)

fin= Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL =600

Ω, C

L=50 pF

2.25

4.50

6.00

-2.25

-4.50

-6.00

-50

dB

fin = 1.0 MHz, RL =50

Ω, C

L=10 pF

2.25

4.50

6.00

-2.25

-4.50

-6.00

-40

-

Feedthrough

Noise, Channel

Select Input to

Common O/I

(Figure 7)

VIN

≤ 1 MHz Square Wave (t

r = tf = 6 ns)

Adjust RL at Setup so that IS= 0 A Enable =

GND

RL =600

Ω, C

L=50 pF

2.25

4.50

6.00

-2.25

-4.50

-6.00

25

105

135

mVpp

RL =10

Ω, C

L=10 pF

2.25

4.50

6.00

-2.25

-4.50

-6.00

35

145

190

-

Crosstalk

Between Any

Two Switches

(Figure 14)

fin= Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL =600

Ω, C

L=50 pF

2.25

4.50

6.00

-2.25

-4.50

-6.00

-50

dB

fin = 1 MHz, RL =50

Ω, C

L=10 pF

2.25

4.50

6.00

-2.25

-4.50

-6.00

-60

THD

Total Harmonic

Distortion

(Figure 16)

fin= 1 kHz, RL =10 k

Ω, C

L=50 pF

THD = THDMeasured - THDSource

VIS =4.0 VPP sine wave

VIS =8.0 VPP sine wave

VIS =11.0 VPP sine wave

2.25

4.50

6.00

-2.25

-4.50

-6.00

0.10

0.08

0.05

%

* Limits not tested. Determined by design and verified by qualification.

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