SL74HC373 datasheet(4/5 Pages) SLS

Il numero della parte	SL74HC373

Spiegazioni elettronici	Octal 3-State Noninverting Transparent Latch

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Produttore elettronici	SLS [System Logic Semiconductor]

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SL74HC373

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS(C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

25

°C to

-55

°C

≤85°C

≤125°C

Unit

tPLH, tPHL

Maximum Propagation Delay, Input D to Q

(Figures 1 and 5)

2.0

4.5

6.0

125

25

21

155

31

26

190

38

32

ns

tPLH, tPHL

Maximum Propagation Delay , Latch Enable to Q

(Figures 2 and 5)

2.0

4.5

6.0

140

28

24

175

35

30

210

42

36

ns

tPLZ, tPHZ

Maximum Propagation Delay ,Output Enable to Q

(Figures 3 and 6)

2.0

4.5

6.0

150

30

26

190

38

33

225

45

38

ns

tPZL, tPZH

Maximum Propagation Delay , Output Enable to Q

(Figures 3 and 6)

2.0

4.5

6.0

150

30

26

190

38

33

225

45

38

ns

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

2.0

4.5

6.0

60

12

10

75

15

13

90

18

15

ns

CIN

Maximum Input Capacitance

-

10

pF

COUT

Maximum Three-State Output Capacitance

(Output in High-Impedance State)

-

15

pF

Power Dissipation Capacitance (Per Enabled

Output)

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption: PD=CPDVCC

2f+I

CCVCC

36

pF

TIMING REQUIREMENTS (C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

25

°C to

-55

°C

≤85°C

≤125°C

Unit

tSU

Minimum Setup Time, Input D

to Latch Enable

(Figure 4)

2.0

4.5

6.0

25

5.0

30

6.0

40

8.0

7.0

ns

th

Minimum Hold Time,Latch

Enable to Input D

(Figure 4)

2.0

4.5

6.0

5.0

ns

tw

Minimum Pulse Width, Latch

Enable (Figure 2)

2.0

4.5

6.0

60

12

10

75

15

13

90

18

15

ns

tr, tf

Maximum Input Rise and Fall

Times (Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

ns

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