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SL74HC165 Scheda tecnica(PDF) 5 Page - System Logic Semiconductor |
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SL74HC165 Scheda tecnica(HTML) 5 Page - System Logic Semiconductor |
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5 / 7 page  SL74HC165 System Logic Semiconductor SLS TIMING REQUIREMENTS (C L=50pF,Input t r=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55 °C ≤85°C ≤125°C Unit tSU Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load (Figure 4) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tSU Minimum Setup Time, Input SA to Clock (or Clock Inhibit) (Figure 5) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tSU Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit) (Figure 6) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tSU Minimum Setup Time, Clock to Clock Inhibit (Figure 7) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns th Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs (Figure 4) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Clock (or Clock Inhibit) to Input SA (Figure 5) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load (Figure 6) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns trec Minimu m Recovery Time, Clock to Clock Inhibit (Figure 7) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tw Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 1) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tw Minimum Pulse Width, Serial Shift/Parallel Load (Figure 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns |
Codice articolo simile - SL74HC165 |
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