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SL4029BN Scheda tecnica(PDF) 4 Page - System Logic Semiconductor

Il numero della parte SL4029BN
Spiegazioni elettronici  Presettable Up/Down Counter
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Produttore elettronici  SLS [System Logic Semiconductor]
Homepage  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL4029BN Scheda tecnica(HTML) 4 Page - System Logic Semiconductor

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SL4029B
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L=50pF, RL=200k
Ω, Input t
r=tf=20 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
≥-55°C
25
°C
≤125°C
Unit
tmax
Maximum Clock Frequency (Figure 1)
5.0
10
15
2
4
5.5
2
4
5.5
1
2
2.75
MHz
tPHL, tPLH
Maximum Propagation Delay, Clock to Q
(Figure 1)
5.0
10
15
500
240
180
500
240
180
1000
480
360
ns
tPHL, tPLH
Maximum Propagation Delay, Clock to Carry
Output (Figure 1)
5.0
10
15
560
260
190
560
260
190
1120
520
380
ns
tPHL, tPLH
Maximum Propagation Delay, Preset Enable
to Q (Figure 1)
5.0
10
15
470
200
160
470
200
160
940
400
320
ns
tPHL, tPLH
Maximum Propagation Delay, Preset Enable to
Carry Output (Figure 1)
5.0
10
15
640
290
210
640
290
210
1280
580
420
ns
tPHL, tPLH
Maximum Propagation Delay, Carry Input to
Carry Output (Figure 1)
5.0
10
15
340
140
100
340
140
100
680
280
200
ns
tTHL, tTLH
Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
CIN
Maximum Input Capacitance
-
7.5
pF
FUNCTION TABLE
CONTROL INPUT
LOGIC LEVEL
ACTION
BIN/DEC
(B/D)
H
L
BINARY COUNT
DECADE COUNT
UP/DOWN
(U/D)
H
L
UP COUNT
DOWN COUNT
PRESET ENABLE
(PE)
H
L
JAM IN
NO JAM
CARRY IN (CI)
(CLOCK ENABLE)
H
L
NO COUNTER ADVANCE AT POS.
CLOCK TRANSITION
ADVANCE COUNTER AT POS. CLOCK
TRANSITION


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