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ES51996 Scheda tecnica(PDF) 9 Page - Cyrustek corporation |
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ES51996 Scheda tecnica(HTML) 9 Page - Cyrustek corporation |
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9 / 30 page  ver. 2.8 12/02/03 9 ES51996(6000counts) DMM Analog front end/Insulation The ID byte of ES51996 is header of “110010” followed by a buzzer on/off control bit and R/W bit. The start/stop bit definition is shown on the diagram below. 1.2 Read/Write command description The write command includes one ID byte with four command bytes. If the valid write ID code is received by ES51996 at any time, the write command operation will be enabled. The next table shows the content of write command. Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ID 1 1 0 0 1 0 BUZ R/W=0 W1 SHBP F3 F2 F1 F0 Q2 Q1 Q0 W2 B0 B1 B2 C0 C1 FQ2 FQ1 FQ0 W3 AC 0 0 EXT FS60 LPF1 LPF0 FRES W4 PEAK PCAL IRQ IRV IRR OP0 OP1 EXT_ADP Auxiliary low-resistance detection control bit for Continuity and Diode modes: SHBP Measurement function control bit: F3/F2/F1/F0 Range control bit for V/A/R/C modes: Q2/Q1/Q0 Range control bit for Freq mode: FQ2/FQ1/FQ0 Buzzer frequency selection: B2/B1/B0 Buzzer driver ON/OFF control bit: BUZ ADC conversion rate control bit: C1/C0 AC mode control enable bit: AC PEAK/Calibration mode enable bit: PEAK/PCAL 3dB BW for low-pass-filter selection: LPF1/LPF0 External source for Diode mode control bit: EXT OP configuration control bit: OP1/OP0 Frequency mode input resistance control bit: FRES ADP mode control bit: EXT_ADP ADP DC mode full scale control bit: FS60 Insulation mode control bit: IRQ/IRV/IRR |
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