ADV3205JSTZ datasheet(5/20 Pages) AD

Il numero della parte	ADV3205JSTZ

Spiegazioni elettronici	60 MHz, G = 2, 16 횞 16

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Produttore elettronici	AD [Analog Devices]

Homepage	http://www.analog.com

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Data Sheet

ADV3205

Rev. 0 | Page 5 of 20

TIMING CHARACTERISTICS (PARALLEL MODE)

Table 4.

Limit

Parameter

Symbol

Min

Max

Unit

Parallel Data Setup Time

t1d

20

ns

Address Setup Time

t1a

20

ns

CLK Enable Width

t2

100

ns

Parallel Data Hold Time

t3d

20

ns

Address Hold Time

t3a

20

ns

CLK Pulse Separation

t4

100

ns

CLK-to-UPDATE Delay

t5

0

ns

UPDATE Pulse Width

t6

50

ns

Propagation Delay, UPDATE to Switch On or Off

50

ns

CLK, UPDATE Rise and Fall Times

100

ns

RESET Time

200

ns

1

0

CLK

1

0

A0 TO A3

1

0

D0 TO D4

1 = LATCHED

UPDATE

0 = TRANSPARENT

t6

t5

t1a

t3a

t3d

t1d

t4

t2

Figure 3. Timing Diagram, Parallel Mode

Table 5. Logic Levels

VIH

VIL

VOH

VOL

IIH

IIL

IOH

IOL

RESET, SER/PAR

CLK, D0, D1, D2,

D3, D4, A0, A1, A2,

A3, CE, UPDATE

RESET, SER/PAR

CLK, D0, D1, D2,

D3, D4, A0, A1, A2,

A3, CE, UPDATE

DATA OUT

RESET, SER/PAR

CLK, D0, D1, D2,

D3, D4, A0, A1, A2,

A3, CE, UPDATE

RESET, SER/PAR

CLK, D0, D1, D2,

D3, D4, A0, A1, A2,

A3, CE, UPDATE

DATA OUT

2.0 V min

0.8 V max

2.7 V min

0.5 V max

20 μA max

−400 μA min

−400 μA max

3.0 mA min

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