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6N138S(TB)-V Scheda tecnica(PDF) 7 Page - Everlight Electronics Co., Ltd |
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6N138S(TB)-V Scheda tecnica(HTML) 7 Page - Everlight Electronics Co., Ltd |
7 / 14 page Everlight Electronics Co., Ltd. 7 http://www.everlight.com Document No:DPC-0000019 Rev.2 February 23, 2009 8 PIN DIP LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON PHOTOCOUPLER 6N138 6N139 Fig. 13 Switching Time Test Circuit and Waveform Fig. 14 Common Mode Transient Immunity Test Circuit and Waveform Note: *3 Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the common mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO > 2.0V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO < 0.8V). IF VO 5V 1.5V VOL tPLH tPHL +5V Vo RL 0.1uF 0.1uF Rin IF Monitor IF Pulse Generator Tr=5ns, Zo=50Ω VF CMH: Switch at B (IF=0mA) CML: Switch at A (IF=1.6mA) IF +5V RL 0.1uF VF Vo B A VFF VCM |
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