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AD8052LV Scheda tecnica(PDF) 11 Page - Cadeka Microcircuits LLC. |
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AD8052LV Scheda tecnica(HTML) 11 Page - Cadeka Microcircuits LLC. |
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11 / 14 page  ©2011 CADEKA Microcircuits LLC www.cadeka.com 11 Data Sheet At non-inverting gains other than G = +1, keep Rg below 1kΩ to minimize peaking; thus, for optimum response at a gain of +2, a feedback resistor of 1kΩ is recommended. Figure 5 illustrates the AD8052LV frequency response with both 1kΩ and 2kΩ feedback resistors. Frequency (MHz) 1 10 100 Rf = 2kΩ Rf = 1kΩ G = 2 RL = 2kΩ Vs = +5V Figure 5: Frequency Response vs. Rf Power Dissipation Power dissipation should not be a factor when operating under the stated 2kΩ load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it’s intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150°C. To calculate the junction temperature, the package thermal resistance value ThetaJA (ӨJA) is used along with the total die power dissipation. TJunction = TAmbient + (ӨJA × PD) Where TAmbient is the temperature of the working environment. In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. PD = Psupply - Pload Supply power is calculated by the standard power equation. Psupply = Vsupply × IRMS supply Vsupply = VS+ - VS- Power delivered to a purely resistive load is: Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, Rloadeff in Figure 3 would be calculated as: RL || (Rf + Rg) These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from PD = PQuiescent + PDynamic - PLoad Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power can be calculated as above with the desired signal amplitudes using: (VLOAD)RMS = VPEAK / √2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDYNAMIC = (VS+ - VLOAD)RMS × ( ILOAD)RMS Assuming the load is referenced in the middle of the power rails or Vsupply/2. The AD8052LV is short circuit protected. However, this may not guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. Figure 6 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available. 0 0.5 1 1.5 2 2.5 -40 -20 0 20 40 60 80 Ambient Temperature (°C) SOIC-8 Figure 6. Maximum Power Derating |
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