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AZP51 Scheda tecnica(PDF) 5 Page - Arizona Microtek, Inc |
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AZP51 Scheda tecnica(HTML) 5 Page - Arizona Microtek, Inc |
5 / 9 page Arizona Microtek, Inc. AZP51 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider www.azmicrotek.com +1-480-962-5881 5 Request a Sample May 2012, Rev 2.1 DUAL SUPPLY LVPECL OUTPUT TERMINATION The standard LVPECL loads are a pair of 50 Ω resistors connected between the outputs and V DD-2.0V (Figure 4). The resistors provide both the DC and the AC loads, assuming 50 Ω interconnect. If an additional supply is available within the application, a four resistor termination configuration is possible (Figure 5). VDD (+3.3 V) Vbp M1 M2 M3 M4 D Vbn M5 21.1mA 21.1mA 16mA Q Q 82 Ω 82 Ω 21.1mA - High 5.1mA - Low External Circuitry Output Stage 130 Ω 130 Ω VDD (+3.3 V) Figure 5 - Dual Supply Output Termination THREE RESISTOR TERMINATION Another termination variant eliminates the need for the additional supply (Figure 6). Alternately three resistors and one capacitor accomplish the same termination and reduce power consumption. VDD (+3.3 V) Vbp M1 M2 M3 M4 D Vbn M5 21.1mA 21.1mA 16mA Q Q 50 Ω 50 Ω 21.1mA - High 5.1mA - Low External Circuitry Output Stage 50 Ω 0.01µF Figure 6 - Three Resistor Termination |
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