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LA6242H Scheda tecnica(PDF) 5 Page - Sanyo Semicon Device |
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LA6242H Scheda tecnica(HTML) 5 Page - Sanyo Semicon Device |
5 / 9 page LA6242H No.7814-5/9 Pin Functions Pin No. Pin name Pin description 1 VIN1−A Channel 1 input amplifier A inverting input 2 VIN1+A Channel 1 input amplifier A non-inverting input 3 VCCP1 Channels 1 and 2: power stage power supply 4 VO1+ Channel 1 output ( +) 5 VO1− Channel 1 output ( −) 6 VO2+ Channel 2 output ( +) 7 VO2− Channel 2 output ( −) 8 VO3+ Channel 3 output ( +) 9 VO3− Channel 3 output ( −) 10 VO4+ Channel 4 output ( +) 11 VO4− Channel 4 output ( −) 12 VCCP2 Channels 3 and 4: power stage power supply 13 VIN4 Channel 4 input 14 VIN4G Channel 4 input (gain adjustment) 15 VIN3 Channel 3 input 16 VIN3G Channel 3 input (gain adjustment) 17 VIN2 Channel 2 input 18 VIN2G Channel 2 input (gain adjustment) 19 REGIN Base connection of external PNP transistor 20 REGOUT Regulator error amplifier input (+) 21 VCCS Signal system power supply 22 VREFIN Reference voltage input 23 MUTE Output on/off control 24 VIN1-SW Channel 1 input operational amplifier switching 25 SGND Signal system ground 26 VIN1+B Channel 1 amplifier B non-inverting input 27 VIN1−B Channel 1 amplifier B inverting input 28 VIN1 Channel 1 input and input operational amplifier output Note: • The center frame (FR) is used as the power system ground (P-GND). Along with the signal system ground (SGND), this level must be the lowest potential in the system. • The VCCS (signal system power supply), VCCP1, and VCCP2 (output stage power supplies) must be shorted together externally. |
Codice articolo simile - LA6242H_09 |
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Descrizione simile - LA6242H_09 |
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