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FM28V100-TG Scheda tecnica(PDF) 5 Page - Ramtron International Corporation |
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FM28V100-TG Scheda tecnica(HTML) 5 Page - Ramtron International Corporation |
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5 / 13 page  FM28V100 - 128Kx8 FRAM Rev. 1.2 May 2010 Page 5 of 13 Precharge Operation The precharge operation is an internal condition in which the state of the memory is prepared for a new access. Precharge is user-initiated by driving at least one of the chip enable signals to an inactive state. The chip enable must remain inactive for at least the minimum precharge time tPC. Precharge is also activated by changing the upper addess A(16:3). The current row is first closed prior to accessing the new row. The device automatically detects an upper order address change which starts a precharge operation, the new address is latched, and the new read data is valid within the tAA address access time. Refer to the Read Cycle Timing 1 diagram on page 9. Likewise a similar sequence occurs for write cycles. Refer to the Write Cycle Timing 3 diagram on page 11. The rate at which random addresses can be issued is tRC and tWC, respectively. Endurance The FM28V100 is capable of being accessed at least 1014 times – reads or writes. An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A16-A3 and column addresses by A2-A0. The array is organized as 16K rows of 8-bytes each. The entire row is internally accessed once whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. The user may choose to write CPU instructions and run them from a certain address space. The table below shows endurance calculations for 256-byte repeating loop, which includes a starting address, 7 page mode accesses, and a CE precharge. The number of bus clocks needed to complete an 8-byte transaction is 8+1 at lower bus speeds, but 9+2 at 33MHz due to initial read latency and an extra clock to satisfy the device’s precharge timing constraint tPC. The entire loop causes each byte to experience only one endurance cycle. F-RAM read and write endurance is virtually unlimited even at 33MHz system bus clock rate. Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop Bus Freq (MHz) Bus Cycle Time (ns) 256-byte Transaction Time ( µµµµs) Endurance Cycles/sec. Endurance Cycles/year Years to Reach 1014 Cycles 33 30 10.56 94,690 2.98 x 1012 33.5 25 40 12.8 78,125 2.46 x 1012 40.6 10 100 28.8 34,720 1.09 x 1012 91.7 5 200 57.6 17,360 5.47 x 1011 182.8 |
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