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FM25V10-GTR Scheda tecnica(PDF) 11 Page - Ramtron International Corporation |
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FM25V10-GTR Scheda tecnica(HTML) 11 Page - Ramtron International Corporation |
11 / 16 page FM25V10 - 1Mb SPI FRAM Rev. 2.0 May 2010 Page 11 of 16 Figure 15. Read Serial Number Endurance The FM25V10 and FM25VN10 devices are capable of being accessed at least 1014 times, reads or writes. An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A16-A3 and column addresses by A2-A0. See Block Diagram (pg 2) which shows the array as 16K rows of 64-bits each. The entire row is internally accessed once whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. The table below shows endurance calculations for 64-byte repeating loop, which includes an op-code, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop. F-RAM read and write endurance is virtually unlimited even at 40MHz clock rate. Table 7. Time to Reach 100 Trillion Cycles for Repeating 64-byte Loop SCK Freq (MHz) Endurance Cycles/sec. Endurance Cycles/year Years to Reach 1014 Cycles 40 73,520 2.32 x 1012 43.2 20 36,760 1.16 x 1012 86.4 10 18,380 5.79 x 1011 172.7 5 9,190 2.90 x 1011 345.4 S C D Q Byte 7 Byte 6 . . . C3h . . . . . . . Byte 1 Byte 0 |
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