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FM24V05-G Scheda tecnica(PDF) 7 Page - Ramtron International Corporation |
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FM24V05-G Scheda tecnica(HTML) 7 Page - Ramtron International Corporation |
7 / 16 page FM24V05 - 512Kb I2C FRAM Rev. 2.0 May 2010 Page 7 of 16 issues a start condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a ‘1’. The operation is now a current address read. S A Slave Address 1 Data Byte 1 P By Master By FM24V05 Start Address Stop Acknowledge No Acknowledge Data Figure 7. Current Address Read S A Slave Address 1 Data Byte 1 P By Master By FM24V05 Start Address Stop Acknowledge No Acknowledge Data Data Byte A Acknowledge Figure 8. Sequential Read S A Slave Address 1 Data Byte 1 P By Master By FM24V05 Start Address Stop No Acknowledge Data S A Slave Address 0 Address MSB A Start Address Acknowledge Address LSB A Figure 9. Selective (Random) Read S A Slave Address 1 Data Byte 1 P By Master By FM24V05 Start & Enter HS-mode Address Stop & Exit HS-mode No Acknowledge Data S 1 Start Acknowledge X X X 1 0 0 0 0 HS-mode command No Acknowledge Figure 10. HS-mode Current Address Read S A Slave Address 0 Data Byte A P By Master By FM24V05 Start & Enter HS-mode Address & Data Stop & Exit HS-mode S 1 Start Acknowledge X X X 1 0 0 0 0 HS-mode command Address MSB A Address LSB A No Acknowledge Figure 11. HS-mode Byte Write |
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