ISL59911IRZ-EVALZ datasheet(9/17 Pages) INTERSIL

Il numero della parte	ISL59911IRZ-EVALZ

Spiegazioni elettronici	250MHz Triple Differential Receiver/ Equalizer with I2C Interface

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Produttore elettronici	INTERSIL [Intersil Corporation]

Homepage	http://www.intersil.com/cda/home

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ISL59911

9

FN7548.0

September 2, 2011

0x0B

Blue Channel Manual Offset (0x00)

(Default is auto-calibrated)

6:0

Blue Offset

0x00: -400mV Offset

0x7F: +400mV Offset

(Output Referred)

7

Manual Offset Control

(Blue)

0: Offset is auto calibrated - value in bits 6:0 is ignored

1: Offset DAC set to value in bits 6:0

0x0C

Offset Calibration Control (0x00)

0

Start Cal

Set to 1 to initiate offset calibration. Bit is reset to 0 when

calibration is complete (in ~3µs or less).

1

Cal Mode

0: Analog inputs disconnected from external pins and

internally shorted together during calibration.

1: Analog inputs remain connected to external circuitry

during calibration. Useful for calibrating out system-wide

offsets. External offsets of up to ~±160mV can be

eliminated.

2

Short Inputs

0: Normal operation

1: Inputs shorted together (independent of the Cal Mode bit)

0x0D - 0x12 Reserved

7:0

Reserved

Reserved. Do not write anything to these addresses.

0x13

Initialization

7:0

Initialization

After initial power on, write 0x06 to this register,

followed by a write of 0x00 to this register.

NOTE: All registers are read/write unless otherwise noted.

Register Listing (Continued)

ADDRESS

REGISTER (DEFAULT VALUE)

BIT(S)

FUNCTION NAME

DESCRIPTION

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