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BD3873FS Scheda tecnica(PDF) 3 Page - Rohm |
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BD3873FS Scheda tecnica(HTML) 3 Page - Rohm |
3 / 16 page Technical Note 3/15 www.rohm.com 2010.10 - Rev.A © 2010 ROHM Co., Ltd. All rights reserved. BD3870FS,BD3871FS,BD3872FS,BD3873FS SC (CLOCK) thd thd th ts ts1 th1 tsd twc twh twd tw1 tsu DATA DATA LATCH 90% 90% 90% 90% 10% 10% 10% 90% 90% 90% 90% 90% 10% 10% 10% twc End with Low SI DATA LATCH ● Timing chart 1) Signal Timing Conditions ・ Data is read on the rising edge of the clock. ・ Latch is read out on the falling edge of the clock. ・ Latch signal must end with the LOW state. ・ To avoid malfunctions, clock and data signals must terminate with the LOW state. 1byte=10bit Fig.1 Parameter Symbol Limits Unit Min. Typ. Max. Minimum Clock Width Twc 2.0 - - µs Minimum Data Width twd 2.0 - - µs Minimum Latch Width Tw1 2.0 - - µs Data Set-up Time (DATA CLK) Tsd 1.0 - - µs Data Hold Time (CLK DATA) Thd 1.0 - - µs Latch Set-up Time (CLK LATCH) Ts1 1.0 - - µs Latch Hold Time (DATA LATCH) Th1 1.0 - - µs Latch Low Set-up Time Ts 1.0 - - µs Latch Low Hold Width Twh 2.0 - - µs 2) Voltage Conditions for Control Signals Parameter Limits Unit Condition Min. Typ. Max. (≦Vcc) “H” Input Voltage 2.2 - 5.5 V Vcc=4.5 to 9.5V “L” Input Voltage 0 - 1.0 V Vcc=4.5 to 9.5V |
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