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STK14C88-C45I Scheda tecnica(PDF) 3 Page - Cypress Semiconductor |
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STK14C88-C45I Scheda tecnica(HTML) 3 Page - Cypress Semiconductor |
3 / 20 page STK14C88 Document Number: 001-52038 Rev. *C Page 3 of 20 Pin Configurations Figure 1. Pin Diagram - 32-Pin 300 Mil SOIC/CDIP Figure 2. Pin Diagram - 32-Pin 450 Mil LCC A14 A12 A7 A6 DQ0 DQ1 DQ2 A3 A2 A1 VCAP A13 A8 A9 A11 A10 DQ7 DQ6 VSS A0 NC 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 E A5 NC A4 32 31 30 29 VCC HSB W DQ5 DQ3 DQ4 G (TOP) A6 A3 A5 A4 DQ0 A2 A1 A0 A10 DQ7 A8 A9 A11 NC NC A13 E G (TOP) Pin Descriptions Pin Name I/O Description A14-A0 Input Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array. DQ7-DQ0 I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM. E Input Chip Enable: The active low E input selects the device. W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E. G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tristate. VCC Power Supply Power: 5.0V, +10%. HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (optional connection). VCAP Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. VSS Power Supply Ground. NC No Connect Unlabeled pins have no internal connections. [+] Feedback |
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