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ISLA216P20 Scheda tecnica(PDF) 7 Page - Intersil Corporation

Il numero della parte ISLA216P20
Spiegazioni elettronici  12-Bit, 500MSPS ADC Programmable Built-in Test Patterns
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Produttore elettronici  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISLA216P20 Scheda tecnica(HTML) 7 Page - Intersil Corporation

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ISLA212P50
7
FN7843.1
May 25, 2011
Table of Contents
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin-Compatible Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Descriptions - 72 Ld QFN, LVDS Mode . . . . . . . . . . . . . 2
Pin Descriptions - 72 Ld QFN, CMOS Mode . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2E Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . 14
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 17
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Temperature Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2E Requirements and Restrictions . . . . . . . . . . . . . . . . . 21
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Active Run State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Power Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
FS/4 Filter (Notch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Nyquist Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Configurability and Communication . . . . . . . . . . . . . . .22
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . 22
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . .25
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Device Configuration/Control . . . . . . . . . . . . . . . . . . . .25
Address 0x60-0x64: I2E initialization . . . . . . . . . . . . .28
Global Device Configuration/Control . . . . . . . . . . . . . .28
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
A/D Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Split Ground and Power Planes . . . . . . . . . . . . . . . . . .35
Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . .35
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . 38


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