Motore di ricerca datesheet componenti elettronici |
|
TDA21220 Scheda tecnica(PDF) 11 Page - Infineon Technologies AG |
|
TDA21220 Scheda tecnica(HTML) 11 Page - Infineon Technologies AG |
11 / 26 page TDA21220 Theory of Operation Preliminary Data Sheet 11 Revision 1.9, 2011-03-31 5 Theory of Operation The TDA21220 incorporates a high performance gate driver, one high-side power MOSFET and one low-side power MOSFET in a single 40 lead QFN package. The advantages of this arrangement are found in the areas of increased performance, increased efficiency and lower overall package and layout inductance.This module is ideal for use in Synchronous Buck Regulators either as a stand-alone power stage that can deliver up to 50 A or with an interleaved approach for higher current loads. The power MOSFETs are tailored for this device. The gate driver is a robust high-performance driver rated at the switching node for DC voltages ranging from -1 V to +25 V. The closely coupled driver and MOSFETs enable efficiency improvements that are hard to match using discrete components. The power density for transmitted power of this approach is approximately 40 W within a 36 mm 2 area. 5.1 Driver Characteristics The gate driver of the TDA21220 has 2 voltage inputs, VCIN and VDRV. VCIN is the 5 V logic supply for the driver. VDRV is also 5 V and is used to drive the High and Low Side MOSFETs. Ceramic capacitors should be placed very close to these input voltage pins to decouple the sensitive control circuitry from a noisy environment. The MOSFETs selected for this application are optimized for 5 V gate drive, thus giving the end user optimized high load as well as light load efficiency. The reference for the power circuitry including the driver output stage is PGND and the reference for the gate driver control circuit (VCIN) is CGND. Referring to the Block Diagram page, VCIN is internally connected to the UVLO circuit and for VCIN voltages less than required for proper circuit operation will provide shut-down. VDRV supplies both, the floating high side drive and the low-side drive circuits. An active boot circuit for the high side gate drive is also included. A second UVLO circuitry, sensing the BOOT voltage level, is implemented to prevent false GH turn on during insufficient power supply level condition (BOOT Cap charging/discharging sequence). During undervoltage both GH and GL are driven low actively; further passive pull-down (500 k ) is placed across gate-source of both FETs. Figure 4 Internal Output Signal from UVLO Unit VCIN “H” “L” VUVLO_F VUVLO_R UVLO Output Logic Level Shutdown Enable |
Codice articolo simile - TDA21220 |
|
Descrizione simile - TDA21220 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |