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AD8253 Scheda tecnica(PDF) 11 Page - Analog Devices |
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AD8253 Scheda tecnica(HTML) 11 Page - Analog Devices |
11 / 20 page Preliminary Technical Data AD8426 Rev. PrD | Page 11 of 20 THEORY OF OPERATION A3 R2 24.7kΩ R1 24.7kΩ A1 A2 Q2 Q1 –IN +IN +VS –VS R3 50kΩ R4 50kΩ R5 50kΩ RB RB +VS –VS VOUT REF NODE 1 NODE 2 RG VBIAS +VS –VS +VS –VS NODE 4 NODE 3 R6 50kΩ DIFFERENCE AMPLIFIER STAGE GAIN STAGE ESD AND OVERVOLTAGE PROTECTION ESD AND OVERVOLTAGE PROTECTION –VS Figure 7. Simplified Schematic ARCHITECTURE The AD8426 is based on the classic three op amp topology. This topology has two stages: a gain stage (preamplifier) to provide differential amplification, followed by a difference amplifier to remove the common-mode voltage. Figure 7 shows a simplified schematic of one of the instrumentation amplifiers in the AD8426. The first stage works as follows: to maintain a constant voltage across the bias resistor, RB, A1 must keep Node 3 at a constant diode drop above the positive input voltage. Similarly, A2 keeps Node 4 at a constant diode drop above the negative input voltage. Therefore, a replica of the differential input voltage is placed across the gain setting resistor, RG. The current that flows across this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 out- puts. Note that, in addition to a gained differential signal, the original common-mode signal, shifted a diode drop up, is also still present. The second stage is a difference amplifier, composed of A3 and four 50 kΩ resistors. The purpose of this stage is to remove the common-mode signal from the amplified differential signal. The transfer function of the AD8426 is VOUT = G × (VIN+ − VIN−) + VREF where: G R G kΩ 49.4 1 GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the AD8426, which can be calculated by referring to Table 7 or by using the following gain equation: 1 kΩ 49.4 G R G Table 7. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG Calculated Gain 49.9 kΩ 1.990 12.4 kΩ 4.984 5.49 kΩ 9.998 2.61 kΩ 19.93 1.00 kΩ 50.40 499 Ω 100.0 249 Ω 199.4 100 Ω 495.0 49.9 Ω 991.0 The AD8426 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the AD8426 specifications to determine the total gain accu- racy of the system. When the gain resistor is not used, gain error and gain drift are minimal. REFERENCE TERMINAL The output voltage of the AD8426 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to level- shift the output so that the AD8426 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or −VS by more than 0.3 V. For the best performance, source impedance to the REF terminal should be kept below 2 Ω. As shown in Figure 8, the reference terminal, REF, is at one end of a 50 kΩ resistor. Additional impedance at the REF terminal adds to this 50 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be computed by 2 × (50 kΩ + RREF)/100 kΩ + RREF. |
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