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FSB50250S_0705 Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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FSB50250S_0705 Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page 2 www.fairchildsemi.com FSB50250S Rev. B Pin Descriptions Note: Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside SPM®. External connections should be made as indicated in Fig- ure 2 and 5. Figure 1. Pin Configuration and Internal Block Diagram (Bottom View) Pin Number Pin Name Pin Description 1 COM IC Common Supply Ground 2 VB(U) Bias Voltage for U Phase High Side FRFET Driving 3 VCC(U) Bias Voltage for U Phase IC and Low Side FRFET Driving 4 IN(UH) Signal Input for U Phase High-side 5 IN(UL) Signal Input for U Phase Low-side 6 VS(U) Bias Voltage Ground for U Phase High Side FRFET Driving 7 VB(V) Bias Voltage for V Phase High Side FRFET Driving 8 VCC(V) Bias Voltage for V Phase IC and Low Side FRFET Driving 9 IN(VH) Signal Input for V Phase High-side 10 IN(VL) Signal Input for V Phase Low-side 11 VS(V) Bias Voltage Ground for V Phase High Side FRFET Driving 12 VB(W) Bias Voltage for W Phase High Side FRFET Driving 13 VCC(W) Bias Voltage for W Phase IC and Low Side FRFET Driving 14 IN(WH) Signal Input for W Phase High-side 15 IN(WL) Signal Input for W Phase Low-side 16 VS(W) Bias Voltage Ground for W Phase High Side FRFET Driving 17 P Positive DC–Link Input 18 U Output for U Phase 19 NU Negative DC–Link Input for U Phase 20 NV Negative DC–Link Input for V Phase 21 V Output for V Phase 22 NW Negative DC–Link Input for W Phase 23 W Output for W Phase COM VCC LIN HIN VB HO VS LO COM VCC LIN HIN VB HO VS LO COM VCC LIN HIN VB HO VS LO (1) COM (2) V B(U) (3) V CC(U) (4) IN (UH) (5) IN (UL) (6) V S(U) (7) V B(V) (8) V CC(V) (9) IN (VH) (10) IN (VL) (11) V S(V) (12) V B(W) (13) V CC(W) (14) IN (WH) (15) IN (WL) (16) V S(W) (17) P (18) U (19) N U (20) N V (21) V (22) N W (23) W |
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